Extreme ultraviolet (EUV) lithography is a next-generation optical lithography technology for the sub-22 nanometer (nm) semiconductor technology node. In contrast to conventional optical lithography utilized in current generation semiconductor manufacturing processes, such as DUV or ArF (“193 nm”) optical lithography, EUV lithography utilizes a reflective mask which selectively reflects and absorbs extreme ultraviolet radiation. EUV radiation having a wavelength of approximately 10-20 nanometers is typically utilized.
Because of the extremely small printed feature sizes inherent in EUV lithography technology, it is important to maintain the EUV lithography mask to be as free of defects and contaminants as possible, as even very small defects and contaminants present in the EUV lithography mask may result in significant feature defects on the substrate in turn affecting the finished product's yield. In developing methods of cleaning EUV lithography masks, several challenges are faced.
The method of cleaning must be gentle enough so as not to damage the mask features, yet still provide for effective particle and contamination removal from the mask. Selectivity issues must be dealt with in the development of cleaning chemistries due to the different absorptive and reflective surfaces present on the mask. Furthermore, many current cleaning methods involve the use of high temperatures to increase the efficiency of the wet cleaning chemistry. However, repeated exposure of the EUV lithography mask to high temperatures can cause thermally-induced defects, such as defects in the reflective portions of the mask due to diffusion of materials between layers. Such internal defects cannot be removed, and may therefore diminish the lifetime of the EUV lithography mask.
FIG. 1 illustrates a graph showing number of defects in substrates produced from a given EUV lithography mask versus the number of use cycles for the mask. At an initial use cycle count C0 the EUV lithography mask produces substrates which are substantially defect deficient, having a defect level D0. As the number of use cycles increases, the level of defects produced by the EUV lithography mask rises until reaching a maximum tolerated defect level Dmax. When the level of defects produced by the EUV lithography mask reaches Dmax, the mask is then cleaned. The level of defects reaches Dmax at a use cycle count C1, at which point the EUV lithography mask is cleaned. This cleaning of the EUV lithography mask significantly improves the defect level of the mask, bringing the level of defects produced by the mask down to a level D1.
However, the level D1 is not as low as D0, thus indicating that it is not possible to clean the EUV lithography mask to the same level as originally possible upon initial use of the mask at use cycle count C0. This may be the result of several factors, such as a buildup of non-removable surface defects, such as defects within the layered structure of the EUV lithography mask. Or it may not be possible to fully clean particles and chemicals from the EUV lithography mask without damaging or otherwise compromising the EUV lithography mask in other ways. This may be due to selectivity issues and limitations due to the fragility of the patterned structure of the absorber layer of the EUV lithography mask.
Because the EUV lithography mask is not cleaned to the same level as before, fewer use cycles are enabled before the defect level produced by the mask once again reaches Dmax, and requires another cleaning. This is shown at use cycle C2, wherein the defect level produced by the mask has reached Dmax again, so as to require another cleaning. The number of use cycles from C1 to C2 is less than the number of use cycles from C0 to C1 because the defect level produced by the mask at C1 is greater than that at C0, as it was not possible to clean the EUV lithography mask at use cycle C1 to the defect level D0 of use cycle C0, but only to the defect level D1.
Similarly, at use cycle C2, the EUV lithography mask can only be cleaned to a defect level D2, which is greater than the defect level D1, which is the defect level to which the EUV lithography mask was cleaned at use cycle C1. A subsequent buildup of defects to the defect level Dmax occurs in fewer use cycles than the preceding buildup to the same level. As shown, the number of use cycles from C2 to C3 is less than that from C1 to C2, indicating that fewer use cycles were required to reach a defect level of Dmax again. Alternatively, a mask may be cleaned successfully over several iteration and then fail catastrophically upon one given clean due to pitting in one of the layers and go from D1 immediately to above Dmax.
As can be seen, the inability to adequately clean the EUV lithography mask results in an accumulating number of defects produced by the mask over time, which in turn shortens the time between cleans in successive cycles of operation in order to not compromise yield. As the time between cleans is shortened, the EUV lithography mask is potentially exposed to high temperatures more frequently, which results in further increases in diffusion-related defects within the EUV lithography mask. All of this causes a reduction in the useful lifetime of the EUV lithography mask before it is required to be replaced.
It is in this context that embodiments of the invention arise.